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Silicon Image's patented VRS® ClearView™ technology scales and cleans video from any source, optimizing it for HD displays.
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Silicon Image will release its second quarter 2014 financial results after the market closes on July 30, 2014.
The RAID controller IP core is silicon-proven intellectual property (IP) for integration into system-on-chip (SoC) products, reducing overall bill-of-material costs and requiring less board space than discrete chip solutions. By partnering with Silicon Image, IP customers can achieve quicker time-to-market through shorter design cycles and faster testing and compliance. The IP core features a SATA digital host interface and two digital eSATA capable device ports. By leveraging proven performance RAID functionality, users can easily speed up (RAID0) or add redundancy (RAID1) with virtually no software development.
Digital Controller for RAID 0 (Fast), RAID 1 (Safe) and JBOD
The silicon-proven RAID controller IP core is a low-cost solution for applications including external storage enclosures, system boards, backup storage, PC motherboards, flash storage, surveillance DVR, media services, and set-top-boxes (STBs). It supports JBOD and the following RAID modes: FAST (RAID0) and SAFE (RAID1) configurations. RAID mode configuration can be accomplished through a System Management Bus (SMBus)-based GUI or dedicated signaling for true software-free implementation.
Advanced features include enhanced sector recovery and automatic data repair to provide higher levels of protection for critical data. In RAID0 and RAID1 modes, cascading the IP block enables support for up to four drives. In this configuration, a RAID10 set may also be created. Management parameters can be customized using the Manufacturing Utility or through customer applications built using the optional Software Development Kit. The IP core supports aggressive power-down modes when drive(s) are idle or not present.
The IP core is available with optional SATA Transport and Link logic blocks to support easy integration into customer's SoC, providing a modified SAPIS interface for connection to a SATA PHY.